TC551402J-20 Datasheet (Toshiba)

TC551402J-20, CMOS SRAM

The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device.

The mode (x1/x4) is selected by the input level of pin 17 (81/84).

The T

TC551402J-20 Features

* low power dissipation when the SRAM is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. It is suitable for use in high speed applications such as cache memory, high speed storage, and main memory. All inputs and outputs are TIL compatible. The TC551402J