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TC518512PI-10 - SILICON GATE CMOS PSEUDO STATIC RAM

Download the TC518512PI-10 datasheet PDF. This datasheet also covers the TC518512PI-80 variant, as both devices belong to the same silicon gate cmos pseudo static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC518512PI is a 4M bit high speed CMOS pseudo static RAMorganized as 524,288 words by 8 bits.

The TC518512PI utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacityJ:!!,9h speed and low power storage.

Features

  • a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface. The TC518512PI is guaranteed over an operating temperature range of -40 - 85°C. The TC518512PI is available in a 32-pin, 0.6 inch width plastic DIP and a small outline plastic flat package. Features.
  • Organization: 524,288 words x 8 bits.
  • Single 5V power supp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC518512PI-80-Toshiba.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC518512PI-10
Manufacturer Toshiba
File Size 277.58 KB
Description SILICON GATE CMOS PSEUDO STATIC RAM
Datasheet download datasheet TC518512PI-10 Datasheet

Full PDF Text Transcription

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TOSHIBA SILICON GATE CMOS 524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM 11:518512PI/F1~/10 Description The TC518512PI is a 4M bit high speed CMOS pseudo static RAMorganized as 524,288 words by 8 bits. The TC518512PI utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacityJ:!!,9h speed and low power storage. The TC518512PI operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two types of refreshing - auto refresh and self refresh. The TC518512PI features a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface.
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