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TC518129AFWL-10LV - SILICON GATE CMOS PSEUDO STATIC RAM

Download the TC518129AFWL-10LV datasheet PDF. This datasheet also covers the TC518129APL-80LV variant, as both devices belong to the same silicon gate cmos pseudo static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC518129A-LV is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits.

The TC518129A-LV utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage.

Features

  • a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface. A CS standby mode interface is incorporated in the TC518129A-LV family, with the CE2 pin in the TC518128A-LV family changed to a CS pin. The TC518129A-LV is available in a 32-pin, 0.6 inch width plastic.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC518129APL-80LV-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA TC5I8I29APLIAFLIAFWL-80LVII0LVI I2LV TC5I8I29AF1L-80LVII0LVI I2LV SILICON GATE CMOS 131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The TC518129A-LV is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129A-LV utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The TC518129A-LV operates from a single power supply of 3.135V - 5.5V Refreshing is supported by a refresh (RFSro input which enables two types of refreshing - auto refresh and self refresh. The TC518129A-LV features a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RIW thus simplifying the microprocessor interface.
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