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TC74VHC9273P - Octal D-Type Flip-Flop

Download the TC74VHC9273P datasheet PDF. This datasheet also covers the TC74VHC9273FK variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: fmax = 195 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Function compatible with 74VHC273.
  • Input terminals are at the opposite side of Output terminals TC74VHC9273P TC74VHC9273FK Weight DIP20-P-300-2.54A VSSOP20-P-0030-0.50 : 1.30 g ( typ. ) : 0.03 g ( typ. ).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74VHC9273FK_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74VHC9125P 5-bit Universal Schmitt Buffer Toshiba
TC74VHC9126FK 5-bit Universal Schmitt Buffer Toshiba
TC74VHC9126P 5-bit Universal Schmitt Buffer Toshiba
TC74VHC912FK 5-bit Universal Schmitt Buffer Toshiba
TC74VHC9151FK 9-Bit Schmitt Buffer Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74VHC9273FK Octal D-Type Flip-Flop
TC74VHC9273FT CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC9541FK Octal Universal Schmitt Buffer
TC74VHC9541FT Octal Universal Schmitt Buffer
TC74VHC9541P Octal Universal Schmitt Buffer

Full PDF Text Transcription

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TC74VHC9273P/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC9273P, TC74VHC9273FK Octal D-Type Flip Flop with Clear The TC74VHC9273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held “L”, the Q outputs are at a low logic level independent of the other inputs. The CLR input and CK input have hysteresis between the positive-going and negative-going thresholds.
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