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TC55NEM208AFPN - TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Description

The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.

Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ± 10% power supply.

Features

  • Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 5 V ± 10% Power down features using CE . Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of.
  • 40° to 85°C Standby Current (maximum):20 µA.
  • Access Times (maximum): TC55NEM208AFPN/AFTN 55 Access Time 55 ns 55 ns 30 ns 70 70 ns 70 ns 35 ns CE Access.

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Datasheet Details

Part number TC55NEM208AFPN
Manufacturer Toshiba
File Size 134.83 KB
Description TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet download datasheet TC55NEM208AFPN Datasheet

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www.DataSheet4U.com TC55NEM208AFPN/AFTN55,70 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ± 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs.
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