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CXD1961AQ - DVB-S Frontend IC (QPSK demodulation + FEC)

General Description

The CXD1961AQ is a single chip DVB compliant Satellite Broadcasting Frontend IC, including dual A/D converter for analog baseband I/Q input, QPSK demodulator, Viterbi decoder Reed-Solomon decoder and Energy Dispersal descrambler.

It is suitable for use in a DVB Integrated Receiver Decoder.

Key Features

  • Dual 6 bit A/D converter Absolute Maximum Rating (Ta = 25°C, GND = 0V).
  • QPSK demodulator.
  • Power Supply VDD.
  • 0.5 to +4.6 V Multi-symbol rate operation.
  • Input Voltage VIN.
  • 0.5 to VDD + 0.5 V Nyquist Roll off filter (α = 0.35).
  • Output Voltage VOUT.
  • 0.5 to VDD + 0.5 V Clock recovery circuit.
  • I/O Voltage VI/O.
  • 0.5 to VDD + 0.5 V Carrier recovery circuit.
  • CPU I/F pin Vcpuif.
  • 0.5 to +5.5 V AGC contro.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CXD1961AQ DVB-S Frontend IC (QPSK demodulation + FEC) Preliminary For the availability of this product, please contact the sales office. Description The CXD1961AQ is a single chip DVB compliant Satellite Broadcasting Frontend IC, including dual A/D converter for analog baseband I/Q input, QPSK demodulator, Viterbi decoder Reed-Solomon decoder and Energy Dispersal descrambler. It is suitable for use in a DVB Integrated Receiver Decoder. 100 pin QFP (Plastic) Features • Dual 6 bit A/D converter Absolute Maximum Rating (Ta = 25°C, GND = 0V) • QPSK demodulator • Power Supply VDD –0.5 to +4.6 V Multi-symbol rate operation • Input Voltage VIN –0.5 to VDD + 0.5 V Nyquist Roll off filter (α = 0.35) • Output Voltage VOUT –0.5 to VDD + 0.5 V Clock recovery circuit • I/O Voltage VI/O –0.