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SI53322 - Low-Jitter LVPECL Fanout Clock Buffers

Description

2.

The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers.

All devices except the Si53326 and Si53328 have a universal input that accepts most common differential or LVCMOS input signals.

Features

  • include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance. KEY.

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Datasheet preview – SI53322

Datasheet Details

Part number SI53322
Manufacturer Silicon Laboratories
File Size 1.08 MB
Description Low-Jitter LVPECL Fanout Clock Buffers
Datasheet download datasheet SI53322 Datasheet
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Full PDF Text Transcription

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Si53320-28 Data Sheet Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL Outputs from Any-Format Input and Wide Frequency Range from DC up to 1250 MHz The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and redundant clocking applications. These devices feature typical ultra-low jitter characteristics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Builtin LDOs deliver high PSRR performance and reduce the need for external components, simplifying low-jitter clock distribution in noisy environments. The Si53320–28 family is available in multiple configurations, with some versions offering a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation.
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