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M368L6423ETN-A2 - DDR SDRAM Unbuffered Module

General Description

Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 (for x72 module) Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip

Key Features

  • 2 I/O 3 I/O 4 I/O 5 D15 D3/D0/D5 VDDSPD SPD Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA VREF VSS VDD/VDDQ D11/D8/D13 D0 - D15 D0 - D15 D0 -.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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256MB, 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 256Mb E-die with 64/72-bit ECC/Non ECC Revision 1.1 August. 2003 Rev. 1.1 August. 2003 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (April, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August.