K7P401822M Description
K7P403622M K7P401822M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev.No.History Rev.0..
Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD
Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Gl.
K7P401822M Features
* 128Kx36 or 256Kx18 Organizations.
* 3.3V Core Power Supply.
* LVTTL Input and Output Levels.
* Differential, PECL Clock Inputs K, K.
* Synchronous Read and Write Operation
* Registered Input and Registered Output
* Internal Pipeline Latches t
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