Description
K7A803609A K7A801809A Document Title 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev.
The K7A803609A and K7A801809A are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium an.
Features
* Synchronous Operation.
* 2 Stage Pipelined operation with 4 Burst.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* 3.3V+0.165V/-0.165V Power Supply.
* I/O Supply Voltage 3.3V+0.165V/-0.165V for
Applications
* GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address
