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Gre r Pro
STT08L01
Ver 1.2
S a mHop Microelectronics C orp.
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V DSS
100V
FEATURES Super high dense cell design for low R DS(ON). Rugged and reliable. Surface Mount Package.
ID
2.5A
R DS(ON) (m ) Max
225 @ VGS=10V 360 @ VGS=4.5V
D
G G S
STT SERIES SOT - 223
S
ABSOLUTE MAXIMUM RATINGS ( T A=25 °C unless otherwise noted ) Symbol VDS VGS ID IDM EAS PD TJ, TSTG Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous -Pulsed
b d a
Limit 100 ±20 TA=25°C TA=70°C 2.5 2.0 10 12 TA=25°C TA=70°C 3 1.
STT08L01 Datasheet
