IMSA110 Datasheet (STMicroelectronics) - IMAGE AND SIGNAL PROCESSING SUB.SYSTEM

IMSA110, IMAGE AND SIGNAL PROCESSING SUB.SYSTEM

The IMSA110 consists of a configurable array of multiply-accumulators, three programmable length 1120 stage shift registers, a versatile post-processing unit and a microprocessor interface for configuration and control purposes.

The comprehensive on-chip facilities make a single device capable of de

IMSA110 IMAGE AND SIGNAL PROCESSING SUB SYSTEM .

1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS (0 1120 STAGES) 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW ON-CHIP POST PROCESSOR FOR DATA TRANSFORMATION FULLY CASCADABLE IN WINDOW SIZE AND ACCURACY 20 MHZ DATA THROUGHPUT (420 MOPS) SIGNED/UNSIGNED DATA AND COEFFICIENTS MICROPROCESSOR INTERFACE