74LVQ125 Datasheet - STMicroelectronics

74LVQ125 QUAD BUS BUFFERS 3-STATE

The LVQ125 is a low voltage CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/8 74LVQ125 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBO.

® 74LVQ125 QUAD BUS BUFFERS (3-STATE) s s s s s s s s s s s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION.

74LVQ125 Datasheet (61.60 KB)