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STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STLC5432 Description

STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRELIMINARY DATA ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD) ISDN PRIMARY ACCE.
STLC5432, CMOS device, interfaces the multiplex system to the physical CEPT Transmission link at 2048Kb/s.

STLC5432 Features

* te) All digital inputs All digital inputs 2.2 XTAL1 input XTAL1 input VCC-0.5 IL = 7mA for pins AL0, AL1, INT, DOUT, HCR, LCR. All other digital outputs: IL = 1mA IL = 7mA for pins AL0, AL1, 2.4 INT, DOUT, HCR, LCR. 2.4 All other digital outputs: IL = 1mA Any digita

STLC5432 Applications

* FOUR LOOPBACK MODES FOR TESTING PSEUDO RANDOM SEQUENCE GENERATOR AND ANALYZER FOR ON-LINE, OFFLINE AND AUTOTEST CLOCK RECOVERY CIRCUITRY ON CHIP 64 BYTE ELASTIC MEMORY FOR TIME COMPENSATION AND AUTOMATIC FRAME AND SUPERFRAME ALIGNMENT 32 ON CHIP REGISTERS FOR CONFIGURATIONS, TESTING, ALARMS, FAULT A

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2Mbit CEPT PRIMARY RATE CONTROLLER DEVICE ST Microelectronics
ST Microelectronics STLC5432-like datasheet