S80016LK7 - SYNCHRONOUS DRAM

Datasheet Details

The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.

es: Intel PC-100 (3-3-3) or PC133 (3-3-3) compatible Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access precharge time Programmable burst lengths: 1, 2, or 4 using Interleaved Burst Addressing Auto Precharge and Auto Refresh modes 64ms, 4,096-cycle refresh quad-row refresh, (15.6µs/row) Self Refresh mode 1 LVTTL-compatible inputs and outputs Single +3.3V ±0.3.

📁 S80016LK7 Similar Datasheet

Other Datasheets by SPECtek

Published: Oct 4, 2005 |