R7F102G4C3CNP - MCU

Renesas

Datasheet Details

Ultra-low power consumption technology.
VDD = single power supply voltage of 1.6 to 5.5 V.
HALT mode.
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core.
CISC architecture with 3-stage pipeline.
The minimum instruction execution time can be changed from high to ultra-low speed. - High speed: 0.03125 µs at 32-MHz operation with the high-speed on-chip oscillator clock - Ultra-low speed: 30.5 µs at 32.768-kHz.

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Published: Jan 17, 2025 |