R7F100GFN - MCU

Renesas

Datasheet Details

Ultra-low power consumption technology.
VDD = single power supply voltage of 1.6 to 5.5 V.
HALT mode.
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.768 kHz operation with the subsystem c.

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Published: Jan 18, 2025 |