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R5F51405ADFM - 32-bit RX MCU

This page provides the datasheet information for the R5F51405ADFM, a member of the R5F51406ADFN 32-bit RX MCU family.

Features

  • 32-bit RXv2 CPU core.
  • Maximum operating frequency: 48 MHz Capable of 204 Coremark in operation at 48 MHz.
  • Enhanced DSP instructions: 32-bit multiply-accumulate instructions, and 16-bit multiply-subtract instructions are supported.
  • On-chip FPU: 32-bit single-precision floating point compliant with IEEE-754.
  • On-chip divider that operated at the fastest of two clock cycles.
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length ins.

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Full PDF Text Transcription

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Datasheet RX140 Group R01DS0379EJ0120 Renesas MCUs Rev.1.20 Nov 22, 2024 48-MHz, 32-bit RX MCUs, on-chip FPU, 204 Coremark, up to 256-KB flash memory, up to 36 pins capacitive touch sensing unit, up to 9 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply, Encryption functions (optional) Features ■ 32-bit RXv2 CPU core  Maximum operating frequency: 48 MHz Capable of 204 Coremark in operation at 48 MHz  Enhanced DSP instructions: 32-bit multiply-accumulate instructions, and 16-bit multiply-subtract instructions are supported.
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