R5F51138ADFP - 32-Bit MCU

Renesas

Datasheet Details

32-bit RX CPU core.
32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32bit × 32-bit operations.
Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with five-stage pipeline.
Variable-length instruction format, ultra-compact cod.

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Published: Jan 1, 2016 |