R5F51115AGFM - 32 MHz 32-bit RX MCUs

Renesas

R5F51115AGFM Datasheet Preview — Preview of R5F51115AGFM PDF

Datasheet Details

Part number	R5F51115AGFM
Manufacturer	Renesas ↗
File Size	1.04 MB
Description	32 MHz 32-bit RX MCUs
Datasheet	R5F51115AGFM_Renesas.pdf

R5F51115AGFM Product details

Description

Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit × 32-bit →

Features

32-bit RX CPU core.
32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with five-stage pipeline.
Variable-length instruction format, ultra-compact code.
On-chip debuggi.

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Published: Dec 23, 2013 |