R5F12008ANS - MCU

Renesas

Datasheet Details

Low power consumption technology.
VDD = single power supply voltage of 2.4 to 5.5 V.
HALT mode.
STOP mode RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to low speed (1.0 μs: @ 1 MHz operation).
Address space: 1 MB.
General-purpose registers: (8-bit register × 8) × 4 banks.
On-chip RAM: 1 KB Code flash memory.

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Published: Aug 28, 2023 |