87016I - LVCMOS/LVTTL Clock Generator

Datasheet Summary

Description

The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator.

The device has four banks of four outputs and each bank can be independently selected for 1 or 2 frequency operation.

Features

Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs).
Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input.
CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
CLK0 supports the following input types: LVCMOS, LVTTL.
Maximum output frequency: 250MHz.
Independent bank control for ÷1 or ÷2 operation.
Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation.

Renesas

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Datasheet Details

Part number	87016I
Manufacturer	Renesas
File Size	605.84 KB
Description	LVCMOS/LVTTL Clock Generator
Datasheet	87016I Datasheet
Additional preview pages of the 87016I datasheet.

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Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator 87016I DATASHEET Description The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has four banks of four outputs and each bank can be independently selected for 1 or 2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for 1 or 2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually.

Published: May 26, 2020 |