Datasheet4U Logo Datasheet4U.com

8304I - 1-to-4 LVCMOS/LVTTL Fanout Buffer

Description

The 8304I is a low skew, 1-to-4 Fanout Buffer.

operating supply modes (V ).

Features

  • Four LVCMOS / LVTTL outputs.
  • LVCMOS clock input.
  • CLK can accept the following input levels: LVCMOS, LVTTL.
  • Maximum output frequency: 166MHz.
  • Output skew: 60ps (maximum).
  • Part-to-part skew: 650ps (maximum).
  • Small 8 lead SOIC package saves board space.
  • 3.3V input, outputs may be either 3.3V or 2.5V supply modes.
  • -40°C to 85°C ambient operating temperature.
  • Available in lead-free (RoHS 6) compliant package B.

📥 Download Datasheet

Datasheet Details

Part number 8304I
Manufacturer Renesas
File Size 349.81 KB
Description 1-to-4 LVCMOS/LVTTL Fanout Buffer
Datasheet download datasheet 8304I Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
830 SILICON 28V HYPERABRUPT VARACTOR DIODES Zetex Semiconductors
830-1A-12xx Mini Power Automotive Relay OEN
8300 High Density Polyethylene TAISOX
8300M3 Display Excel
830154I-08 Over-Voltage Tolerant 1.5V 1:4 Fanout Buffer IDT

Other Datasheets by Renesas

Part Number Description
8302 LVCMOS / LVTTL Fanout Buffer
83023I Differential-to-LVCMOS Translator/Buffer
83026I Differential-to-LVCMOS/LVTTL Fanout Buffer
83026I-01 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer
83052I Single-Ended Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Low Skew, 1-to-4 LVCMOS/LVTTL Fanout Buffer 8304I Data Sheet GENERAL DESCRIPTION The 8304I is a low skew, 1-to-4 Fanout Buffer. The 8304I is characterized at full 3.3V for input V , and mixed 3.3V and 2.5V for output DD operating supply modes (V ). Guaranteed output and part-to-part DDO skew characteristics make the 8304I ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES • Four LVCMOS / LVTTL outputs • LVCMOS clock input • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency: 166MHz • Output skew: 60ps (maximum) • Part-to-part skew: 650ps (maximum) • Small 8 lead SOIC package saves board space • 3.3V input, outputs may be either 3.3V or 2.
Published: |