HYI39SC128160FE - 128-MBit Synchronous DRAM

Name: HYI39SC128160FE
SKU: HYI39SC128160FE-624366

Qimonda

Datasheet Details

output circuits are synchronized with the positive edge of an externally supplied clock.

Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: PG.
TSOPII.
54 400 mil width This chapter lists all main features of the product family HY[B/I]39S128[8.

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Published: Sep 10, 2008 |