Description
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute high frequency Timing-Safe™ clocks
memory interface systems.General Block Diagram
PLL CLKIN
DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3
PLL CLKIN
MUX
DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3
PCS3P624Z05B/C
CLKOUTA4 CLKOUT4 S2 S1 Select Input Decoding CLKOUTB1 CLKOUTB2 CLKOUTB3
PCS3P624Z09B/C
CLKOUTB4
PulseCore Semiconductor Corporation 1715 S.Bascom Ave Suite 200 Campbell, CA 95008
Tel: 408-879-9077
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Features
- High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 50MHz - 100MHz Multiple low skew Timing-safe™ Outputs: PCS3P624Z05: 5 Outputs PCS3P624Z09: 9 Outputs.
- External Input-Output Delay Control option Supply Voltage: 3.3V±0.3V Commercial and Industrial temperature range Packaging Information: ASM3P624Z05: 8 pin SOIC, and TSSOP ASM3P624Z09:16 pin SOIC, and TSSOP.
- True Drop-in Solutio.