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A2S56D40CTP - 256Mb DDR SDRAM

Datasheet Summary

Description

A2S56D30CTP is a 4-bank x 8,388,608-word x 8bit, A2S56D40CTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

  • - Vdd=Vddq=2.5V ± 0.2V power supply for -6,-75. -Vdd=Vddq=2.6V ± 0.1V power supply for -5. - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strob (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address).

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Datasheet Details

Part number A2S56D40CTP
Manufacturer Powerchip Semiconductor
File Size 620.59 KB
Description 256Mb DDR SDRAM
Datasheet download datasheet A2S56D40CTP Datasheet
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www.DataSheet4U.com 256Mb DDR SDRAM Specification A2S56D20CTP A2S56D30CTP A2S56D40CTP Powerchip Semiconductor Corp. No.12, Li-Hsin Rd.1, Science-based Industrial Park, Hsin-Chu Taiwan, R.O.C. TEL: 886-3-5795000 FAX: 886-3-5792168 256Mb DDR Synchronous DRAM Powerchip Semiconductor Corp. www.DataSheet4U.com A2S56D20CTP (4-bank x 16,777,216 - word x 4-bit) A2S56D30CTP (4-bank x 8,388,608 - word x 8-bit) A2S56D40CTP (4-bank x 4,194,304 - word x 16-bit) ORDERING INFORMATION Order Part Number Frequency Speed(ns) Type Standard Low Power Pb-Free Low Power Package and Pb-Free -G5L 400mil TSOP-2 200MHz 5 A2S56D20/30/40 CTP -5 -5L -G5 166MHz 6 A2S56D20/30/40 CTP -6 -6L -G6 -G6L 400mil TSOP-2 400mil TSOP-2 133MHz 7.
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