74HCT73 Datasheet (Philips) - Dual JK flip-flop

74HCT73, Dual JK flip-flop

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).

The 74HC73 is speciﬁed in compliance with JEDEC standard no.

7A.

The 74HC is a dual negative-edge triggered JK ﬂip-ﬂop featuring individual J, K, clock (nCP) and reset (nR) inputs; also compleme

74HCT73 Features

* s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Speciﬁed from

* 40 °C to +80 °C and from

* 40 °C to +125 °C. Philips Semiconductors 74HC73 Dual JK