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74HC5555 - Programmable delay timer

General Description

The 74HC/HCT5555 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

24-stage binary counter integra

Key Features

  • Positive and negative edge triggered.
  • Retriggerable or non-retriggerable.
  • Programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio.
  • Divide-by range of 2 to 224.
  • Direct reset terminates output pulse.
  • Very low power consumption in triggered start mode.
  • 3 oscillator operating modes:.
  • RC oscillator.
  • Crystal oscillator.
  • External oscillator.
  • Device is unaffected by varia.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT5555 Programmable delay timer with oscillator Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Programmable delay timer with oscillator FEATURES • Positive and negative edge triggered • Retriggerable or non-retriggerable • Programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio • Divide-by range of 2 to 224 • Direct reset terminates output pulse • Very low power consumption in triggered start mode • 3 oscillator operating modes: – RC