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74F395 - 4-bit cascadable shift register

General Description

The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs.

The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input.

D3) into

Key Features

  • 4-bit parallel load shift register.
  • Independent 3-State buffer outputs, Q0.
  • Q3.
  • Separate Qs output for serial expansion.
  • Asynchronous Master Reset.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs, Q0–Q3 • Separate Qs output for serial expansion • Asynchronous Master Reset DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0–D3) into the register synchronous with the High-to-Low transition of the Clock input (CP).