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74F256 - Dual addressable latch

General Description

The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table).

In the addressable latch mode, data at the Data inputs is written into the addressed latches.

Key Features

  • Combines dual demultiplexer and 8-bit latch.
  • Serial-to-parallel capability.
  • Output from each storage bit available.
  • Random (addressable) data entry.
  • Easily expandable.
  • Common reset input.
  • Useful as dual 1-of-4 active High decoder.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74F256 Dual addressable latch Product specification IC15 Data Handbook 1988 Nov 29 Philips Semiconductors Philips Semiconductors Product specification Dual addressable latch 74F256 FEATURES • Combines dual demultiplexer and 8-bit latch • Serial-to-parallel capability • Output from each storage bit available • Random (addressable) data entry • Easily expandable • Common reset input • Useful as dual 1-of-4 active High decoder DESCRIPTION The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches.