PLL205-54 Datasheet (PhaseLink) - Programmable Clock Generator

PLL205-54, Programmable Clock Generator

Name VDD(1:5) VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP/ WDRESET# CPU_STOP AGP_STOP REF_STOP PCI(0:8) Number 1,5,15,23,33,31 48 41 2,8,12,19,32, 37,40,45,51 3 4 42 43 44 52 53 10,11,13,14, 16,17,18,20,21 Type P P P P I O I B I I I O Description Power Supplies.

(See Power Group on page1) Power supply

PLL205-54 Features

* PIN CONFIGURATION e e

* Generates all clock frequencies for VIA KT266 h chipset. S a

* Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI. D .

* w Enhanced PCI Output Drive selectable by I2C.

* w One 48MHz c