PLL205-16 Datasheet (PhaseLink) - Programmable Clock Generator

PLL205-16, Programmable Clock Generator

Name VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP# CPU_STOP AGP_STOP N/C PCI(0:8) SEL24_48#/PCI0 Number 1 5 15,23 25 40 33 2,8,12,19,29, 32,37,43 3 4 34 35 36 44 45 10,11,13,14, 16,17,18,20,21 10 Type P P P P P P P I O I I I I O B Description Power supply for REF(0:1), REF_F and crys

PLL205-16 Features

* PIN CONFIGURATION e e frequencies for VIA KT266

* Generates all clock h chipset. S a

* Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and D 10 PCI. .

* w Enhanced PCI Output Drive selectable by I2C.

* w One 48MHz c