MC100EP51 - 3.3V / 5V ECL D Flip-Flop

Product Overview

ON Semiconductor

Datasheet Details

Part number	MC100EP51
Manufacturer	ON Semiconductor
File Size	346.53 KB
Description	3.3V / 5V ECL D Flip-Flop
Datasheet	MC100EP51 Datasheet
Additional preview pages of the MC100EP51 datasheet.

Product details

Description

The MC10/100EP51 is a differential clock D flip flop with reset. flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

Features

350 ps Typical Propagation Delay.
Maximum Frequency > 3 GHz Typical.
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V.
NECL Mode Operating Range: VCC = 0 V with VEE =.
3.0 V to.
5.5 V.
Open Input Default State.
Safety Clamp on Inputs.
These Devices are Pb.
Free and are RoHS Compliant www. onsemi. com 8 1 SOIC.
8 D SUFFIX CASE 751 8 1 TSSOP.
8 DT SUFFIX CASE 948R 1 DFN8 MN SUFFIX C.

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Published: Apr 9, 2007 |