10EL34 Datasheet (ON Semiconductor)

10EL34, MC10EL34

PIN CLK EN MR VBB Q0 Q1 Q2 FUNCTION Diff Clock Inputs Sync Enable Master Reset Reference Output Diff ÷2 Outputs Diff ÷4 Outputs Diff ÷8 Outputs FUNCTION TABLE * * * * * 50ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization 75

MOTOROLA SEMICONDUCTOR TECHNICAL DATA ÷2, ÷4, ÷8 Clock MC10EL34 MC100EL34 Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal.

In addition, by using the VBB o