Description
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.
O I
O O
I O
Ip Ip Ip A/D1 D D D D A A A A A A A A D D D D Description System reset input (LOW -level reset) Chip address set 1 Chip address set 2 Digital supply Left-channel audio output Left-channel audio input Analog supply Left-channel reference voltage (0.5V D D ).
Features
- s s
PINOUT
(Top View)
s s s
s
s s
Stereo inputs and outputs Attenuation function.
- 2-channel independent control.
- 1.0 dB/step over 80 steps.
- 0 to.
- 80 dB range Mute function 3-wire serial data control (MDT, MCK, MLEN) Chip addressing (up to 4 devices can be connected in parallel) Low noise.
- 0.003 % THD + noise.
- 12 µVrms residual noise 2.5 to 3.6 V single power supply Silicon-gate CMOS process
RSTN ADRS1 ADRS2 DVDD LOUT LIN AVDD VRL
1
16.
SM6451_NipponPrecisionCircuitsInc.pdf
