DM86LS62 - Dual Rank 8-Bit TRI-STATE Shift Register

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National

Datasheet Details

Part number	DM86LS62
Manufacturer	National
File Size	157.99 KB
Description	Dual Rank 8-Bit TRI-STATE Shift Register
Datasheet	DM86LS62 Datasheet
Additional preview pages of the DM86LS62 datasheet.

Product details

Description

These circuits are TRI-STATE edge-triggered 8-bit I O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes parallel load from I O pins to register ‘‘A’’ parallel transfer down from register ‘‘A’’ to serial shift register ‘‘B’’ parallel transfer up from shift register ‘‘B’’ to register ‘‘A’’ serial shift of register ‘‘B’’ or exchange data between register ‘‘A’’ and shift register ‘‘B’’ Since the registers are edge-triggered by the po

Features

Y Y Y Y Y Y Y Y Y Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output high impedance state does not impede any other mode of operation 8-bit I O pins are TRI-STATE buffers Typical shift frequency is 36 MHz Typical power dissipation is 305 mW All control inputs are active when in an ‘‘L’’ logic state Devices can be cascaded into N-bit word Connection Diagram Dual-In-Line Package Pin.

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Published: Aug 6, 2005 |