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DS92LV0412 - 5 - 50 MHz Channel Link II Serializer/Deserializer

Download the DS92LV0412 datasheet PDF. This datasheet also covers the DS92LV0411 variant, as both devices belong to the same 5 - 50 mhz channel link ii serializer/deserializer family and are provided as variant models within a single manufacturer datasheet.

Description

The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair.

Features

  • 5-channel (4 data + 1 clock) Channel Link LVDS parallel.
  • interface supports 24-bit data 3-bit control at 5.
  • 50 MHz AC Coupled STP Interconnect up to 10 meters in length Integrated serial CML terminations AT.
  • SPEED BIST Mode and status pin Optional I2C compatible Serial Control Bus Power Down Mode minimizes power dissipation 1.8V or 3.3V compatible control pin interface >8 kV ESD (HBM) protection -40° to +85°C temperature range.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS92LV0411_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com DS92LV0411 / DS92LV0412 5- 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface PRELIMINARY DS92LV0411 / DS92LV0412 May 26, 2010 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface General Description The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges.
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