CD4015BC Datasheet (National Semiconductor) - Dual 4-Bit Static Shift Register

CD4015BC, Dual 4-Bit Static Shift Register

The CD4015BM CD4015BC contains two identical 4-stage serial-input parallel-output registers with independent ‘‘Data’’ ‘‘Clock ’’ and ‘‘Reset’’ inputs The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition A logic high on

CD4015BC Features

* Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Medium speed operation Fully static design 3 0V to 18V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS 8 MHz (typ ) clock rate VDD b VSS e 10V Applications Y Y Y Serial-input parallel-output data queu