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54C165 - Parallel-Load 8-Bit Shift Register

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Description

The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest-order bit (P7) first New serial data may be entered via the SERIAL DATA (Ds) input Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2 Clock inputs may be used separately or together for co

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