54ABT377 Datasheet (National Semiconductor)

54ABT377, Octal D-Type Flip-Flop

The ’ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered.

The state of each D input, one setup time before the LOW-

54ABT377 Features

* n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’ABT273 for master reset version n See ’ABT373 for transparent latch version n See ’ABT374 for TRI-STATE® version n Output sink capability of 48 mA, source capability o