MCF52277 - Microprocessor

Datasheet Details

Version 2 ColdFire® Core with EMAC.
Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz.
8 Kbytes configurable cache (instruction only, data only, or split instruction/data).
128 Kbytes internal SRAM.
Support for booting from SPI-compatible flash, EEPROM, and FRAM devices.
Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters.
16 channel DMA controller.
16- or 32-bit SDR/DDR controller.

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Published: Oct 6, 2024 |