74LVCH162374A
FEATURES
- ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V
- 5 V tolerant input/output for interfacing with 5 V logic
- Wide supply voltage range of 1.2 to 3.6 V
- plies with JEDEC standard no. 8-1A
- CMOS low power consumption
- MULTIBYTE™ flow-through standard pin-out architecture
- Low inductance multiple power and ground pins for minimum noise and ground bounce
- Direct interface with TTL levels
- All data inputs have bus hold (74LVCH162374A only)
- High impedance when VCC = 0
- Power off disables outputs, permitting live insertion. FUNCTION TABLE See note 1. INPUTS OPERATION MODES n OE Load and read register Latch register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH CP transition. L L H H n CP ↑ ↑ ↑ ↑ n Dn l h l h...
