74ALS112A Dual J-K negative edge-triggered flip-flop

NXP

Description

INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductor.
The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and co.

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Datasheet Specifications

Part number: 74ALS112A
Manufacturer: NXP ↗
File Size: 92.64 KB
Datasheet: 74ALS112A_PhilipsSemiconductors.pdf
Description: Dual J-K negative edge-triggered flip-flop

Features

* individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inpu

Applications

* that are descri

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74ALS112A Dual J-K negative edge-triggered flip-flop NXP

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