MPC992 - LOW VOLTAGE PLL CLOCK DRIVER

Product Overview

Motorola

Datasheet Details

Part number	MPC992
Manufacturer	Motorola
File Size	109.01 KB
Description	LOW VOLTAGE PLL CLOCK DRIVER
Datasheet	MPC992 Datasheet
Additional preview pages of the MPC992 datasheet.

Product details

Description

Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compliment PECL reference clock input (Int Pullup) Internal divider select pins (Int Pullup) Internal flip flop reset, true outputs go LOW (Int Pulldown) MOTOROLA 2 TIMING SOLUTIONS BR1333

Features

to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32.
lead TQFP package to optimize both performance and board density. MPC992 LOGIC.

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Published: Oct 19, 2005 |