MPC930 - LOW VOLTAGE PLL CLOCK DRIVER

Motorola

Datasheet Details

for power conscious portable or “green” designs. The power down pin will seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life. The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the power.
down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock outputs while leaving a subset a.

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Published: Nov 22, 2005 |