MC74F109 Datasheet (Motorola) - DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST SCHOTTKY TTL

MC74F109, DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST SCHOTTKY TTL

MC54/74F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST™ SCHOTTKY TTL CONNECTION DIAGRAM VCC CD2 16 15 CD CD1 J1 1 CD1 2 J1 J2 14 J K2 13 K CP2 SD2 11