Description
3-6 Signal Descriptions  3-9 Internal Register Map  3-13 Address Space Maps  3-14 SECTION 4 CENTRAL PROCESSOR UNIT
4.1 General  4-1 4.2 CPU32 Registers  4-2 4.2.1 Data Registers  4-4 4.2.2 Address Registers  4-5 4.2.3 Program Counter  4-6 4.2.4 Control Registers  4-6 4.2.4.1 Status Register  4-6 4.2.4.2 Alternate Function Code Registers  4-7 4.2.5 Vector Base Register (VBR)  4-7 4.3 Memory Organization  4-7
MC68336/376 USER’S MANUAL MOTOROLA iii
TABLE OF CONTENTS
Paragraph (Continued) Title
Features
- 3-1 Central Processing Unit (CPU32)  3-1 System Integration Module (SIM)  3-1 Standby RAM Module (SRAM)  3-1 Masked ROM Module (MRM)  3-1 10-Bit Queued Analog-to-Digital Converter (QADC)  3-2 Queued Serial Module (QSM)  3-2 Configurable Timer Module Version 4 (CTM4)  3-2 Time Processor Unit (TPU)  3-2 Static RAM Module with TPU Emulation Capability (TPURAM)  3-2 CAN 2.0B Controller Module (TouCAN)  3-3 Intermodule Bus  3-3 System Block Diagram and Pin Assignment Diagrams  3-3 Pin.