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MC14517B - Dual 64-Bit Static Shift Register

Features

  • ut = VOH VDD = VGS VDD = VGS Vout = VOL D C WE Q16 Q32 Q48 Q64 D C WE Q16 Q32 Q48 Q64 D C WE Q16 Q32 Q48 Q64 IOH D C WE Q16 Q32 Q48 Q64 IOL VSS (Output being tested should be in the high.
  • logic state).

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www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, regardless of the state of the write enable input. An output is disabled (open circuited) when the write enable input is high. During this time, data appearing at the data input as well as the 16–bit, 32–bit, and 48–bit taps may be entered into the device by application of a clock pulse. This feature permits the register to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used.
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