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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14035B 4-Bit Parallel-In/Parallel-Out Shift Register
The MC14035B 4–bit shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of a 4–stage clocked serial–shift register with synchronous parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input allows serial–right shifting of data or synchronous parallel loading via inputs DP0 thru DP3. The True/Complement (T/C) input determines whether the outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial “D” input.
MC14035B Datasheet
