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SN54LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54LS112A Description

SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop .

SN54LS112A Features

* individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the trut

SN54LS112A Applications

* All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

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Datasheet Details

Part number
SN54LS112A
Manufacturer
Motorola Inc
File Size
147.34 KB
Datasheet
SN54LS112A_MotorolaInc.pdf
Description
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

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